Workshop on Accelerated Stress Testing & Reliability

Sponsored by the IEEE/CPMT ASTR Committee and Co-Sponsored by UC Santa Cruz

WASHINGTON, DC

OCTOBER 31 - NOVEMBER 2, 2007

ASTR 2007 CONFERENCE THEME:

"Accelerated Life Testing, it's Role, Challenges, Attributes, and Interaction with Qualification Testing"

Over the last few years, Accelerated Stress Testing (AST) has been embraced by an ever widening array of worldwide companies seeking to reconcile the need for the highest quality product with the necessary push for early time-to-market. The purpose of the AST Workshop is to share ideas on better ways of accelerating and detecting hidden defects, flaws, and weaknesses in electronic and electro-mechanical hardware that would result in failures during usage. These techniques are focused on testing electronic hardware to destruction limits and root cause investigation to determine the physics-of-failure. The goal of AST is to produce mature products at market introduction and, in making it robust, the product can be screened for manufacturing defects with high combined stresses (beyond end-use specifications) for shorter lengths of time.

Visit the TC-7 home page